Electronic devices commonly require a direct current (DC) voltage of appropriate level for proper operation. A manufacturer of an electronic device provides for a power signal to be connected to the electronic device, which is used to power the semiconductor packages and other electric components of the electronic device. In many cases, the provided power signal is at a different voltage potential than the voltage required to operate the individual components of the electronic device. The manufacturer will generally provide a power conversion circuit to generate a steady DC voltage signal at a voltage potential usable by the electronic device. Switch-mode power supplies (SMPS) are common due to efficiency advantages.
An SMPS may be located within an electronic device, or located externally and connected to the electronic device by a cable. The cable is coupled to the electronic device using a detachable plug in some embodiments. The plug may include both power and data lines, e.g., when an electronic device is a cell phone, tablet computer, or other mobile device, and power is provided by a Universal Serial Bus (USB) interface. In some embodiments, electronic devices follow the USB Power Delivery (USB-PD) protocol to negotiate a voltage potential for power delivery by an external SMPS.
An SMPS operates by switching an input power signal on and off repeatedly to create a relatively high-frequency power signal. The switched power signal is routed through a transformer or inductor, and then rectified and filtered to create a steady DC power signal. The output power signal is commonly rectified by one or more diodes, or a transistor is used for synchronous rectification.
A circuit diagram for one exemplary embodiment of a flyback SMPS 100 is illustrated in FIG. 1. SMPS 100 is formed by components disposed on a circuit board, printed circuit board, or other substrate 101. In some embodiments, SMPS 100 is split across multiple substrates 101. SMPS 100 is divided into a primary side 102 and a secondary side 104, which are delineated by transformer 105. In non-isolated topologies, an inductor is used instead of transformer 105. Transformer 105 includes a primary winding 106 as part of primary side 102 and a secondary winding 108 as part of secondary side 104. Primary side 102 of SMPS 100 is made up of the components electrically connected to primary winding 106. Secondary side 104 of SMPS 100 is made up of the components electrically connected to secondary winding 108. Transformer 105 provides DC isolation between primary side 102 and secondary side 104. Alternating current (AC) signals through primary winding 106 are transferred to secondary winding 108 by magnetic coupling, while any DC offset is substantially ignored.
Primary side 102 includes a power input at bulk voltage (VBULK) node 110. In some embodiments, VBULK node 110 receives an AC power signal provided by an electric utility at, e.g., 110 or 230 volts AC, which has been rectified. The AC electric signal is routed to a residence, commercial office building, or other premises by power mains, and input to the electronic device including SMPS 100 by plugging the device into a wall outlet. A diode bridge or other rectifier circuit rectifies the input AC main signal to include positive voltage values at VBULK node 110. In other embodiments, a power signal is provided to VBULK node 110 by other means, e.g., from solar cells or a battery pack. A capacitor 111 is coupled between VBULK node 110 and ground node 113 to further filter the input power signal. Ground node 113 operates as the ground reference voltage for the electrical components of primary side 102.
Electric current from VBULK node 110 through primary winding 106 to ground node 113 is turned on and off by primary MOSFET 112. Primary MOSFET 112 includes a drain terminal 115 coupled to primary winding 106 opposite VBULK node 110, a gate terminal coupled to primary flyback controller 120 at circuit node 114 (DRV), and a source terminal coupled to current sense resistor 118 at current sense (CS) node 119. The source and drain terminals of primary MOSFET 112 are conduction terminals, and the gate terminal is a control terminal. Controller 120 turns on, or enables electric conduction through, primary MOSFET 112 by providing a positive voltage potential at the gate terminal of the MOSFET via DRV node 114 coupled to a drive output of the controller. In some embodiments, additional driver circuitry is coupled between controller 120 and the gate of MOSFET 112. When primary MOSFET 112 is turned on, electric current flows from VBULK node 110 to ground node 113 through primary winding 106, primary MOSFET 112, and resistor 118 in series. Controller 120 turns off primary MOSFET 112 by outputting a ground voltage potential to the gate of primary MOSFET 112. While primary MOSFET 112 is off, no significant current flows from VBULK node 110 through primary winding 106.
In the ideal case, an n-channel MOSFET exhibits zero resistance when its gate has a positive voltage potential, and exhibits infinite resistance when its gate is at ground potential. MOSFET 112 is an n-channel MOSFET that operates as a switch opened and closed by a control signal from controller 120 coupled to the MOSFET's gate terminal at DRV node 114. A switch, e.g., MOSFET 112, being closed is also referred to as the switch being “on,” because electric current is able to flow between conduction terminals of the switch. An open switch is referred to as being “off” because current does not flow significantly between the conduction terminals of the switch. While the primary switch of SMPS 100 is illustrated as an n-channel MOSFET, other types of electronically controlled switches, e.g., bipolar-junction transistors (BJTs), p-channel MOSFETs, gallium arsenide transistors, junction gate field-effect transistor, other types of field-effect transistors (FETs), and other types of electronic switches, are used in other embodiments. FETs include source and drain terminals, which are conduction terminals, and a gate terminal as a control terminal. BJTs include emitter and collector terminals, which are conduction terminals, and a base terminal as a control terminal.
Controller 120 determines when to switch primary MOSFET 112 by observing the magnitude of current through primary winding 106. Resistor 118 creates a voltage potential difference between ground node 113 and CS node 119 when electric current flows through the resistor. The voltage potential across resistor 118, as observed at CS node 119, is approximately proportional to the current through primary winding 106. CS node 119 is coupled to a current sense input pin of controller 120. Controller 120 observes the voltage potential at CS node 119 to determine the electric current magnitude through primary winding 106.
While controller 120 has primary MOSFET 112 turned on, electric current through primary winding 106 increases approximately linearly and magnetizes transformer 105. When controller 120 turns off primary MOSFET 112, electric current through primary winding 106 is substantially stopped. The magnetic energy stored in transformer 105 while MOSFET 112 was on is output as electric current through secondary winding 108 while MOSFET 112 is off, creating a positive voltage potential at voltage output (VOUT) node 124 relative to ground node 126. Ground node 126 operates as the ground reference voltage for electrical components of secondary side 104. SMPS 100 is an isolated topology, meaning a separate primary side ground node 113 and secondary side ground node 126 are used. The voltage potential of ground node 126 is allowed to float relative to ground node 113.
The voltage potential at VOUT node 124 charges capacitor 128 and powers additional circuit components of an electronic device connected to SMPS 100 as a load. The cycle repeats when controller 120 turns on primary MOSFET 112 to again magnetize transformer 105. Capacitor 128 provides power to VOUT node 124 while primary MOSFET 112 is on, and transformer 105 is being magnetized. Diode 130 rectifies current through secondary winding 108 by reducing electric current flowing from VOUT node 124 to ground node 126 through secondary winding 108 while transformer 105 is being magnetized from primary side 102.
Feedback is provided from secondary side 104 to primary side 102 by Zener diode 154 and optocoupler 155. Optocoupler 155 includes an LED 156 and a phototransistor 158. If the voltage potential at VOUT node 124 exceeds the Zener voltage of Zener diode 154 summed with the voltage drop of LED 156, current flows from VOUT node 124 to ground node 126 through Zener diode 154 and LED 156 in series. Photons emitted by LED 156 hit phototransistor 158, which turns on the phototransistor and increases the coupling of feedback (FB) node 160 to ground node 113. FB node 160 is coupled to a feedback input pin or terminal of controller 120. Capacitor 159 filters the voltage potential at FB node 160. As current through LED 156 is increased, the coupling of FB node 160 to ground node 113 through phototransistor 158 is increased, and the voltage potential of FB node 160 is further reduced.
The voltage potential at FB node 160 increases as the load on SMPS 100 is reduced, indicating that less power needs to be transferred from primary side 102 to secondary side 104 through transformer 105. Controller 120 delays turning on MOSFET 112 between power cycles for a longer period of time as the load on SMPS 100 is reduced. When the load on SMPS 100 is sufficiently reduced, SMPS 100 transitions from continuous conduction mode (CCM) to discontinuous conduction mode (DCM). In CCM, energy stored in transformer 105 is not completely discharged each power cycle. MOSFET 112 is turned on to begin charging transformer 105 while current is still flowing through secondary winding 108 from ground node 126 to VOUT node 124.
In DCM, the magnetic energy stored in transformer 105 is substantially discharged and current through secondary winding 108 substantially ceases. Diode 130 becomes reverse biased to limit current from VOUT node 124 to ground node 126 through secondary winding 108. While MOSFET 112 remains off, and approximately zero current flows through secondary winding 108, the inductance of primary winding 106 resonates with the output capacitance of MOSFET 112. The resonance creates voltage potential fluctuations at drain terminal 115 of MOSFET 112. Efficiency of SMPS 100 is increased by switching MOSFET 112 back on while the drain voltage of MOSFET 112 is approximately at a minimum, also known as a voltage potential valley. Switching on MOSFET 112 in a drain voltage potential valley reduces switching losses associated with turning on MOSFET 112 by reducing the voltage potential across the conduction terminals of MOSFET 112 during switching.
In a classic fixed frequency SMPS 100, MOSFET 112 is turned back on at a time determined by the voltage potential at FB node 160, without regard to the voltage potential at drain terminal 115 of MOSFET 112. Efficiency of SMPS 100 varies with output power because the timing of switching MOSFET 112 varies. Overall efficiency is higher if MOSFET 112 happens to be turned on near a voltage valley, while the efficiency will be lower if MOSFET 112 is turned on near a voltage peak.
FIG. 2a illustrates switching MOSFET 112 on near a peak of the MOSFET 112 drain voltage. Plot 200 illustrates drain-to-source voltage (VDS) of MOSFET 112 over time. Between time 0 and time 1 in FIG. 2a, MOSFET 112 is on, and VDS is approximately zero due to coupling of drain terminal 115 to ground node 113 through MOSFET 112 and resistor 118. At time 1, controller 120 turns off MOSFET 112, and VDS is positive while energy in transformer 105 is transferred to secondary side 104. Beginning at time 2, the magnetic energy stored in transformer 105 is substantially exhausted and no significant current flows through secondary winding 108. Resonance between primary winding 106 and MOSFET 112 carries VDS to minimums, or valleys, at times 3 and 4, with a peak in between. At time 5, VDS is near a peak, and MOSFET 112 is turned back on. Switching losses of MOSFET 112 are significantly increased due to VDS being near a maximum when MOSFET 112 is turned on at time 5.
Plot 210 in FIG. 2b illustrates VDS with MOSFET 112 switched on during the valley at time 4. A slightly higher output power of SMPS 100 means controller 120 turns on MOSFET 112 a little earlier to provide the needed power transfer to secondary side 104. Turning on MOSFET 112 in a voltage valley increases efficiency by reducing switching losses of MOSFET 112. Plot 220 in FIG. 2c illustrates efficiency of SMPS 100 over a range of output power. As output power fluctuates, SMPS 100 will change from switching in valleys to switching in peaks. Efficiency minimums 224 illustrate power output levels where MOSFET 112 is turned on at VDS peaks, as in FIG. 2a. Efficiency maximums 226 illustrate power output levels where MOSFET 112 is turned on at VDS valleys, as in FIG. 2b 
Designers of switch-mode power supplies seek to maximize efficiency of SMPS 100. One method for increasing efficiency attempts to always switch on MOSFET 112 in VDS valleys. Controller 120 observes VDS and delays turning on MOSFET 112 until a valley is detected. Some controllers wait a certain period of time dictated by the feedback voltage, and then turn on MOSFET 112 when the next valley thereafter is detected. Unfortunately, simply delaying until a valley is observed creates instabilities. When controller 120 switches in a valley, the instantaneous switching cycle is different from the switching cycle imposed by the controller's internal clock. The frequency variation affects output power and the feedback loop reacts by adjusting the peak current. The feedback loop adjustment leads to a new switching event in a different valley from the previous power cycle, either before or after the previous valley. The resulting instability generates acoustic noise and is undesirable.
To increase stability, some valley lockout systems have added hysteresis to the FB node 160 comparison. Once valley switching begins within a certain valley, the output power must move significantly in the opposite direction to return to switching in the previous valley. Using hysteresis to implement valley lockout improves stability, but requires additional comparators implemented on the semiconductor die of controller 120 that increase device size. Moreover, the output power levels at which valley switching occurs depends on various design elements, e.g., input voltage, switching frequency, parasitic inductances, etc. Therefore, difficulty exists for accurately predicting the power level at which the valley number should be changed for all use-cases based on FB node 160. A need exists for a valley lockout mechanism that operates without depending on FB node 160.